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Merge from Tristate branch, part 1 of 2. No functional change intended
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+4
-2
@@ -241,14 +241,16 @@ public:
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//######################################################################
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// Inst class functions
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void V3Inst::pinReconnectSimple(AstPin* pinp, AstCell* cellp, AstNodeModule* modp) {
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AstAssignW* V3Inst::pinReconnectSimple(AstPin* pinp, AstCell* cellp, AstNodeModule* modp) {
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// If a pin connection is "simple" leave it as-is
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// Else create a intermediate wire to perform the interconnect
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// Return the new assignment, if one was made
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// Note this module calles cloneTree() via new AstVar
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AstVar* pinVarp = pinp->modVarp();
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AstVarRef* connectRefp = pinp->exprp()->castVarRef();
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AstBasicDType* pinBasicp = pinVarp->dtypep()->basicp(); // Maybe NULL
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AstBasicDType* connBasicp = NULL;
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AstAssignW* assignp = NULL;
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if (connectRefp) connBasicp = connectRefp->varp()->dtypep()->basicp();
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//
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if (connectRefp
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@@ -268,7 +270,6 @@ void V3Inst::pinReconnectSimple(AstPin* pinp, AstCell* cellp, AstNodeModule* mod
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} else {
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// Make a new temp wire
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//if (1||debug()>=9) { pinp->dumpTree(cout,"in_pin:"); }
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AstAssignW* assignp = NULL;
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AstNode* pinexprp = pinp->exprp()->unlinkFrBack();
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string newvarname = "__Vcellinp__"+cellp->name()+"__"+pinp->name();
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AstVar* newvarp = new AstVar (pinVarp->fileline(), AstVarType::MODULETEMP, newvarname, pinVarp);
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@@ -303,6 +304,7 @@ void V3Inst::pinReconnectSimple(AstPin* pinp, AstCell* cellp, AstNodeModule* mod
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//if (1||debug()) { pinp->dumpTree(cout," out:"); }
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//if (1||debug()) { assignp->dumpTree(cout," aout:"); }
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}
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return assignp;
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}
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//######################################################################
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