Commentary

docs/guide/copyright.rst

@@ -7,10 +7,10 @@ Copyright
 
 The latest version of Verilator is available from https://verilator.org.
 
-Copyright 2003-2026 by Wilson Snyder. Verilator is free software; you
-can redistribute it and/or modify the Verilator internals under the terms
-of either the GNU Lesser General Public License Version 3 or the Perl
-Artistic License Version 2.0.
+Copyright 2003-2026 by Wilson Snyder. Verilator is free software; you can
+redistribute it and/or modify the Verilator internals under the terms of
+either the GNU Lesser General Public License Version 3 or the Perl Artistic
+License Version 2.0.
 
 All Verilog and C++/SystemC code quoted within this documentation file is
 released as Creative Commons Public Domain (CC0). Many example files and

docs/guide/environment.rst

@@ -1,7 +1,7 @@
 .. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-.. _Environment:
+.. _environment:
 
 Environment
 ===========

docs/guide/simulating.rst

@@ -243,8 +243,8 @@ the extracted coverage model:
 Reset transitions are included in the collected data either way. By
 default, :command:`verilator_coverage` summarizes reset-only arcs rather
 than printing them alongside non-reset arcs. Use
-:option:`verilator_coverage --include-reset-arcs` to include
-those arcs in the printed summary and annotated output.
+:option:`verilator_coverage --include-reset-arcs` to include those arcs in
+the printed summary and annotated output.
 
 Annotated output produced by :command:`verilator_coverage --annotate` will
 label FSM points with `fsm_state` and `fsm_arc`, and synthetic fallback

docs/guide/verilating.rst

@@ -269,10 +269,10 @@ core. If there is no affinity already set, on Linux only, Verilator
 attempts to set thread-to-processor affinity in a reasonable way.
 
 Some newer Linux kernels handle thread assignment well. If running
-Verilator on such a system, automatic thread affinity may not be
-beneficial and may even reduce performance. In this case, environment
-variable :vlopt:`VERILATOR_NUMA_STRATEGY` may be set to ``none`` to
-disable automatic thread affinity. For more information, refer to
+Verilator on such a system, automatic thread affinity may not be beneficial
+and may even reduce performance. In this case, environment variable
+:vlopt:`VERILATOR_NUMA_STRATEGY` may be set to ``none`` to disable
+automatic thread affinity. For more information, refer to
 :ref:`Environment`.
 
 For best performance, use the :command:`numactl` program to (when the

docs/internals.rst

@@ -720,15 +720,15 @@ in that process. When ordering code using ``V3Order``, these triggers are
 provided as external domains of these variables. This ensures that the
 necessary combinational logic is triggered after a coroutine resumption.
 
-Every call to a `VlTriggerScheduler`'s `trigger()` method is preempt by
-a call to a proper `__VbeforeTrig` function which evaluates all the necessary
-triggers so, the information about order of suspension/resumption is not lost.
-The triggers necessary to evaluate are ones dependent on the same events
-as the `trigger()` - e.g.: if `triggers()` awaits for event `a` or `b`, then
-every trigger that depends on any of those shall be evaluated. If they wouldn't
-be evaluated and next coroutine after resumption would fire the event `a` then
-it is impossible to get to know whether await or fire on event `a` was called
-first - which is necessary to know.
+Every call to a `VlTriggerScheduler`'s `trigger()` method is preempt by a
+call to a proper `__VbeforeTrig` function which evaluates all the necessary
+triggers so, the information about order of suspension/resumption is not
+lost. The triggers necessary to evaluate are ones dependent on the same
+events as the `trigger()` - e.g.: if `triggers()` awaits for event `a` or
+`b`, then every trigger that depends on any of those shall be evaluated. If
+they wouldn't be evaluated and next coroutine after resumption would fire
+the event `a` then it is impossible to get to know whether await or fire on
+event `a` was called first - which is necessary to know.
 
 There are two functions for managing timing logic called by ``_eval()``:
 
@@ -741,10 +741,10 @@ Thanks to this separation a coroutine:
 
 * awaiting a trigger cannot be suspended and resumed in the same iteration
   (``test_regress/t/t_timing_eval_act.v``) - which is necessary to make
-  Verilator more predictable; this is the reason for introduction of 3rd stage
-  in `VlTriggerScheduler` and thanks to this it is guaranteed that downstream
-  logic will be evaluated before resumption (assuming that the coroutine wasn't
-  already triggered in previous iteration);
+  Verilator more predictable; this is the reason for introduction of 3rd
+  stage in `VlTriggerScheduler` and thanks to this it is guaranteed that
+  downstream logic will be evaluated before resumption (assuming that the
+  coroutine wasn't already triggered in previous iteration);
 * cannot be resumed before it is suspended -
   ``test_regress/t/t_event_control_double_excessive.v``;
 * firing cannot cannot be lost
@@ -2136,13 +2136,14 @@ backtrace. You will typically see a frame sequence something like:
 Bisecting bad transformations
 -----------------------------
 
-If a bad transformation in the internals of Verilator causes a failure only at
-runtime, it can be found fairly automatically by only applying the transform a
-limited number of times, then performing a bisection search over the limit to
-pinpoint the exact transformation that introduces the failure.
+If a bad transformation in the internals of Verilator causes a failure only
+at runtime, it can be found fairly automatically by only applying the
+transform a limited number of times, then performing a bisection search
+over the limit to pinpoint the exact transformation that introduces the
+failure.
 
-To facilitate this an instance of the ``V3DebugBisect`` class can be used in
-conjunction with the ``verilator_bisect`` script.
+To facilitate this an instance of the ``V3DebugBisect`` class can be used
+in conjunction with the ``verilator_bisect`` script.
 
 In the offending algorithm, create a static instance of ``V3DebugBisect``:
 
@@ -2150,30 +2151,31 @@ In the offending algorithm, create a static instance of ``V3DebugBisect``:
 
    static V3DebugBisect s_debugBisect{"TransformName"};
 
-Call the ``stop`` method before applying a transformation, and do not proceed
-if it returns ``false``. Then use ``verilator_bisect`` to search an interval of
-values. You need to provide an arbitrary discriminator command, this should run
-Verilator, then any necessary checks (e.g.: simulation) to detect that the
-failure is still present. It should exit with a non-zero status if the failure
-is still present. The discriminator command can otherwise be arbitrarily
-complex, the actual search limit is passed via environment variables. E.g.:
+Call the ``stop`` method before applying a transformation, and do not
+proceed if it returns ``false``. Then use ``verilator_bisect`` to search an
+interval of values. You need to provide an arbitrary discriminator command,
+this should run Verilator, then any necessary checks (e.g.: simulation) to
+detect that the failure is still present. It should exit with a non-zero
+status if the failure is still present. The discriminator command can
+otherwise be arbitrarily complex, the actual search limit is passed via
+environment variables. E.g.:
 
 ::
 
-  bin/verilator_bisect DfgPeephole 0 1000 test_regress/t/t_myothertest.py
+   bin/verilator_bisect DfgPeephole 0 1000 test_regress/t/t_myothertest.py
 
-An additional command can be run before the discriminator command. E.g.  this
-will run RTLMeter, but first removes its working directory so the models are
-recompiled on every step:
+An additional command can be run before the discriminator command. E.g.
+this will run RTLMeter, but first removes its working directory so the
+models are recompiled on every step:
 
 ::
 
-  bin/verilator_bisect --pre "rm -rf work-bisect" DfgPeephole 0 10000000 \
-    rtlmeter run --cases "..." --workRoot=work-bisect
+   bin/verilator_bisect --pre "rm -rf work-bisect" DfgPeephole 0 10000000 \
+     rtlmeter run --cases "..." --workRoot=work-bisect
 
-When the bisection ends, the first value that makes the discriminator command
-fail is printed, which identifies the exact offending application of the
-transform.
+When the bisection ends, the first value that makes the discriminator
+command fail is printed, which identifies the exact offending application
+of the transform.
 
 Adding a New Feature
 ====================
@@ -2695,6 +2697,7 @@ the terms of either the GNU Lesser General Public License Version 3 or the
 Perl Artistic License Version 2.0.
 
 SPDX-FileCopyrightText: 2003-2026 Wilson Snyder
+
 SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 .. |Logo| image:: https://www.veripool.org/img/verilator_256_200_min.png