luke
/
verilator
mirror of https://github.com/verilator/verilator.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Commentary: Changes update

This commit is contained in:
Wilson Snyder 2025-08-16 09:08:09 -04:00
parent a300bfc538
commit 000d697b51
2 changed files with 6 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
Changes
View File

@ -18,7 +18,7 @@ Verilator 5.039 devel
* Add SPECIFYIGN warning for specify constructs that were previously silently ignored.
* Add PARAMNODEFAULT error, for parameters without defaults.
* Add enum base data type, wire data type, and I/O versus data declaration checking per IEEE.
* Add error on missing and mismatching prototypes (#6206) (#6207). [Alex Solomatnikov]
* Add PROTOTYPEMIS error on missing and mismatching prototypes (#6206) (#6207). [Alex Solomatnikov]
* Add error when trying to assign class object to variable of non-class types (#6237). [Igor Zaworski, Antmicro Ltd.]
* Add error on class 'function static'.
* Add `-DVERILATOR=1` definition to compiler flags when using verilated.mk.
@ -73,7 +73,11 @@ Verilator 5.039 devel
* Fix dynamic cast purity (#6267). [Igor Zaworski, Antmicro Ltd.]
* Fix same variable on the RHS forced to two different LHSs. (#6269). [Artur Bieniek, Antmicro Ltd.]
* Fix spurious VPI value change callbacks (#6274). [Todd Strader]
* Fix stray ']' in Verilog code output for non-constant select (#6277). [Geza Lore]
* Fix variables hiding package imports (#6289). [Johan Wouters]
* Fix DFG circular driver tracing. [Geza Lore]
* Fix no matching function calls for randomized `VlWide` in unpacked and dynamic arrays (#6290). [Mateusz Gancarz]
* Fix PowerPC support (#6292). [Sergey Fedorov]
Verilator 5.038 2025-07-08

1
docs/spelling.txt
View File

@ -471,6 +471,7 @@ Verilog
Vighnesh
Viktor
Vilp
VlWide
Vlip
Vm
Vukobratovic