27 lines
786 B
Python
27 lines
786 B
Python
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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# Should convert the first always into combo and detect cycle
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test.compile(
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fails=True,
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verilator_flags2=["--timing"],
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expect=
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r'%Warning-UNOPTFLAT: t/t_timing_fork_comb.v:\d+:\d+: Signal unoptimizable: Circular combinational logic:'
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)
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test.compile(verilator_flags2=["--exe --main --timing -Wno-UNOPTFLAT"])
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test.execute()
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test.passes()
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