verilator/test_regress/t/t_interface_wire_bad.out

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2025-02-21 22:49:14 +01:00
%Error: t/t_interface_wire_bad.v:17:20: Operator ASSIGNW expected non-interface on Assign RHS but 'a' is an interface.
: ... note: In instance 't'
17 | wire wbad = sub.a;
| ^
%Error: Exiting due to