2012-04-12 21:08:20 -04:00
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// -*- mode: C++; c-file-style: "cc-mode" -*-
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//
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2006-08-26 11:35:28 +00:00
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// DESCRIPTION: Verilator: Verilog Test module
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//
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2026-01-26 20:24:34 -05:00
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2006 Wilson Snyder
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2020-03-21 11:24:24 -04:00
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// SPDX-License-Identifier: CC0-1.0
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2006-08-26 11:35:28 +00:00
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#include <verilated.h>
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2022-08-05 10:56:57 +01:00
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2023-12-19 21:08:30 -05:00
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#include VM_PREFIX_INCLUDE
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2006-08-26 11:35:28 +00:00
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2021-02-16 20:34:44 -05:00
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double sc_time_stamp() { return 0; }
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2019-11-09 20:35:12 -05:00
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int main(int argc, char* argv[]) {
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2006-08-26 11:35:28 +00:00
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Verilated::debug(0);
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2023-01-21 14:05:11 -05:00
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Verilated::commandArgs(argc, argv);
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2023-02-23 06:14:54 -05:00
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VM_PREFIX* topp = new VM_PREFIX;
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2006-08-26 11:35:28 +00:00
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2018-08-25 09:52:45 -04:00
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printf("\nTesting\n");
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2006-08-26 11:35:28 +00:00
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for (int i = 0; i < 10; i++) {
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2019-05-07 22:34:09 -04:00
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topp->clk = 0;
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topp->eval();
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topp->clk = 1;
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topp->eval();
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2006-08-26 11:35:28 +00:00
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}
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if (topp->Rand != 0xfeed0fad) {
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2019-11-09 20:35:12 -05:00
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vl_fatal(__FILE__, __LINE__, "top", "Unexpected value for Rand output\n");
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2006-08-26 11:35:28 +00:00
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}
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2020-11-17 12:37:55 +01:00
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topp->final();
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VL_DO_DANGLING(delete topp, topp);
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2018-08-25 09:52:45 -04:00
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printf("*-* All Finished *-*\n");
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2006-08-26 11:35:28 +00:00
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}
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