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verilator/examples/make_hello_sc/top.v
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// DESCRIPTION: Verilator: Verilog example module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2017 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
2021-11-13 15:01:27 -05:00
// See also https://verilator.org/guide/latest/examples.html"
module top;
initial begin
$display("Hello World!");
$finish;
end
endmodule