39 lines
727 B
Systemverilog
39 lines
727 B
Systemverilog
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// DESCRIPTION: Verilator: Demonstrate struct literal param assignment problem
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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package Some_pkg;
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typedef struct packed {
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int foo;
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} some_struct_t;
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endpackage
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module sub #(
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parameter Some_pkg::some_struct_t the_some_struct
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) ();
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endmodule
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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// finish report
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always @ (posedge clk) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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sub #(
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.the_some_struct(
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Some_pkg::some_struct_t'{
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foo: 1
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}))
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the_sub ();
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endmodule
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