30 lines
568 B
Systemverilog
30 lines
568 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Dan Petrisko.
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// SPDX-License-Identifier: CC0-1.0
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package pkg;
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class cls;
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typedef unknown defu;
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typedef int defi;
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endclass
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endpackage
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module t;
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task tsk;
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begin
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valid1 = 5; // valid statement
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pkg::cls::defi invalid; // invalid statement
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end
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endtask
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endmodule
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typedef struct packed {
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logic clk /*verilator clocker*/;
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logic data;
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} ss_s;
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endmodule
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