99 lines
2.8 KiB
Systemverilog
99 lines
2.8 KiB
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`timescale 1ns/1ps
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// Test constant parameter slicing of unpacked arrays with various slice ranges.
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module issue_desc #(
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parameter int els_p = 1,
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parameter int val_p [els_p+1:2],
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parameter int orig_els = 1
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) ();
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// Drop the lowest index (2) in each recursion: slice [high:3]
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if (els_p > 1) begin : r
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issue_desc #(
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.els_p(els_p-1),
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.val_p(val_p[els_p+1:3]),
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.orig_els(orig_els)
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) x();
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end
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initial begin
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int expected = orig_els - els_p + 1;
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if (val_p[2] !== expected) begin
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$error("DESC wrong value %0d expected %0d in %m", val_p[2], expected);
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$finish;
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end
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$display("%08x (desc %m)", val_p[2]);
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end
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endmodule
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module issue_rev #(
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parameter int els_p = 1,
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parameter int val_p [2:els_p+1],
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parameter int orig_els = 1
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) ();
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// Drop the lowest index (2) in each recursion: slice [3:high]
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if (els_p > 1) begin : r
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issue_rev #(
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.els_p(els_p-1),
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.val_p(val_p[3:els_p+1]),
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.orig_els(orig_els)
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) x();
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end
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initial begin
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int expected = orig_els - els_p + 1;
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if (val_p[2] !== expected) begin
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$error("REV wrong value %0d expected %0d in %m", val_p[2], expected);
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$finish;
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end
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$display("%08x (rev %m)", val_p[2]);
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end
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endmodule
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module issue_def #(
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parameter int els_p = 1,
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// Internal default fill is zero; the test overrides this with DEADBEEF.
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parameter int val_p [els_p+1:2] = '{default:0},
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parameter int orig_els = 1
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) ();
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// Recursively slice off the lowest index (2)
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if (els_p > 1) begin : r
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issue_def #(
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.els_p(els_p-1),
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.val_p(val_p[els_p+1:3]),
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.orig_els(orig_els)
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) x();
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end
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initial begin
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// Expect 32'hDEADBEEF when overridden by the top-level test.
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if (val_p[2] !== 32'hDEADBEEF) begin
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$error("DEF wrong value %0x expected DEADBEEF in %m", val_p[2]);
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$finish;
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end
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$display("%08x (def %m)", val_p[2]);
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end
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endmodule
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module t;
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// For els_p=5, the range [els_p+1:2] is [6:2].
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// Descending initializer: index 6=5,5=4,4=3,3=2,2=1.
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parameter int val_desc [6:2] = '{5,4,3,2,1};
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// Reverse slice initializer: ascending values on [2:6].
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parameter int val_rev [2:6] = '{1,2,3,4,5};
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// Override for default-array test: all elements set to 32'hDEADBEEF on [6:2].
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parameter int val_def [6:2] = '{default: 32'hDEADBEEF};
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issue_desc #(.els_p(5), .val_p(val_desc), .orig_els(5)) iss_desc();
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issue_rev #(.els_p(5), .val_p(val_rev), .orig_els(5)) iss_rev();
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issue_def #(.els_p(5), .val_p(val_def), .orig_els(5)) iss_def();
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initial begin
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#1;
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$write("*-* All Finished *-*\\n");
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$finish;
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end
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endmodule
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