2024-09-08 19:00:03 +02:00
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#!/usr/bin/env python3
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2006-08-26 13:35:28 +02:00
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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2024-01-01 09:19:59 +01:00
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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2020-03-21 16:24:24 +01:00
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# can redistribute it and/or modify it under the terms of either the GNU
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2009-05-04 23:07:57 +02:00
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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2020-03-21 16:24:24 +01:00
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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2006-08-26 13:35:28 +02:00
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2024-09-08 19:00:03 +02:00
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import vltest_bootstrap
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2018-05-08 02:42:28 +02:00
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2024-09-08 19:00:03 +02:00
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test.scenarios('vlt')
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test.top_filename = "t/t_constraint.v"
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2006-08-26 13:35:28 +02:00
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2024-09-08 19:00:03 +02:00
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test.compile()
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2006-08-26 13:35:28 +02:00
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2025-08-10 14:43:04 +02:00
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test.execute(run_env='VERILATOR_SOLVER=someimaginarysolver', fails=True)
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# Not using golden file, as may get spurious pipe messages, see issue #6273
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test.file_grep(test.run_log_filename, r'Unable to communicate with SAT solver')
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2024-09-08 19:00:03 +02:00
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test.passes()
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