29 lines
772 B
Systemverilog
29 lines
772 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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module t (input clk);
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// AstLet and AstProperty are also NodeFTasks, but lets are substituted earlier and properties should be "used" by their asserts so also not deadified
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let nclk = ~clk;
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assert property(@(posedge clk)1);
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function void livefunc();
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endfunction
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task livetask;
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endtask
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// Tasks/functions that are called somewhere will not be deadified
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initial begin
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livefunc();
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livetask();
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$finish;
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end
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// These should be deadified
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function deadfunc();
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endfunction
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task deadtask;
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endtask
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endmodule
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