2025-06-27 00:34:20 +02:00
|
|
|
// DESCRIPTION: Verilator: Verilog Test module
|
|
|
|
|
//
|
2026-01-27 02:24:34 +01:00
|
|
|
// This file ONLY is placed under the Creative Commons Public Domain.
|
|
|
|
|
// SPDX-FileCopyrightText: 2025 Wilson Snyder
|
2025-06-27 00:34:20 +02:00
|
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
|
|
|
|
|
|
package uvm_pkg;
|
|
|
|
|
class uvm_sequence_item;
|
|
|
|
|
endclass
|
|
|
|
|
endpackage
|
|
|
|
|
|
|
|
|
|
package tb_cpu_pkg;
|
|
|
|
|
import uvm_pkg::*;
|
|
|
|
|
class tb_cpu_seq_item extends uvm_sequence_item;
|
|
|
|
|
function void pre_randomize();
|
|
|
|
|
super.pre_randomize();
|
|
|
|
|
endfunction
|
|
|
|
|
function void post_randomize();
|
|
|
|
|
super.post_randomize();
|
|
|
|
|
endfunction
|
|
|
|
|
endclass
|
|
|
|
|
endpackage
|