verilator/test_regress/t/t_preproc_stringend_bad.v

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2019-10-19 03:30:34 +02:00
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2019 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
2019-10-19 03:30:34 +02:00
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