2020-05-10 21:01:43 +02:00
|
|
|
// DESCRIPTION: Verilator: Verilog Test module
|
|
|
|
|
//
|
2026-01-27 02:24:34 +01:00
|
|
|
// This file ONLY is placed under the Creative Commons Public Domain.
|
|
|
|
|
// SPDX-FileCopyrightText: 2020 Wilson Snyder
|
2020-05-10 21:01:43 +02:00
|
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
|
|
2025-09-13 15:28:43 +02:00
|
|
|
module t;
|
2020-05-10 21:01:43 +02:00
|
|
|
|
2025-10-08 03:06:11 +02:00
|
|
|
function int f;
|
|
|
|
|
fork
|
|
|
|
|
;
|
|
|
|
|
join_any // Illegal 13.4.4
|
|
|
|
|
return 0;
|
|
|
|
|
endfunction
|
2020-05-10 21:01:43 +02:00
|
|
|
|
2025-10-08 03:06:11 +02:00
|
|
|
int i;
|
2020-05-10 21:01:43 +02:00
|
|
|
|
2025-10-08 03:06:11 +02:00
|
|
|
initial begin
|
|
|
|
|
i = f();
|
|
|
|
|
end
|
2020-05-10 21:01:43 +02:00
|
|
|
|
|
|
|
|
endmodule
|