2025-12-16 17:21:46 +01:00
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// -*- Verilog -*-
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// DESCRIPTION: Verilator: Verilog Test module
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//
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2026-01-27 02:24:34 +01:00
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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2025-12-16 17:21:46 +01:00
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// SPDX-License-Identifier: CC0-1.0
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// lib.map file:
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library nonelib none.sv, none*.sv, none/; // no matches
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