2025-09-17 14:07:04 +02:00
|
|
|
// DESCRIPTION: Verilator: Verilog Test module
|
|
|
|
|
//
|
2026-01-27 02:24:34 +01:00
|
|
|
// This file ONLY is placed under the Creative Commons Public Domain
|
|
|
|
|
// SPDX-FileCopyrightText: 2025 Antmicro
|
2025-09-17 14:07:04 +02:00
|
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
|
|
|
|
|
|
class base #(
|
2025-12-21 03:46:43 +01:00
|
|
|
type T = int
|
2025-09-17 14:07:04 +02:00
|
|
|
);
|
2025-12-21 03:46:43 +01:00
|
|
|
function void fbase();
|
|
|
|
|
endfunction
|
2025-09-17 14:07:04 +02:00
|
|
|
endclass
|
|
|
|
|
|
|
|
|
|
class ext extends base;
|
2025-12-21 03:46:43 +01:00
|
|
|
function void fext();
|
|
|
|
|
super.fbase();
|
|
|
|
|
endfunction
|
2025-09-17 14:07:04 +02:00
|
|
|
endclass
|