verilator/docs/gen/ex_WIDTHEXPAND_1_fixed.rst

mirror of https://github.com/verilator/verilator.git
.. comment: generated by t_lint_widthexpand_docs_bad
.. code-block:: sv
   :emphasize-lines: 1

     wire [31:0] rd_value = array[{1'b0, rd_addr}];  //<--- Fixed
Split WIDTH warning into WIDTHEXPAND and WIDTHTRUNC (#3900) 2023-02-03 00:25:25 +01:00			`.. comment: generated by t_lint_widthexpand_docs_bad`
Documentation has been rewritten into a book format. 2021-04-12 00:55:06 +02:00			`.. code-block:: sv`
			`:emphasize-lines: 1`

Add wire data type checking per IEEE. 2025-07-20 13:21:30 +02:00			`wire [31:0] rd_value = array[{1'b0, rd_addr}]; //<--- Fixed`