19 lines
492 B
Systemverilog
19 lines
492 B
Systemverilog
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// -*- Verilog -*-
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2019 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// Test requires command line be passed uvm_pkg.sv before this filename
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// verilator lint_off DECLFILENAME
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module t;
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import uvm_pkg::*;
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initial begin
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// verilator lint_off WIDTHTRUNC
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`uvm_info("TOP", "Hello World!", UVM_MEDIUM);
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end
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endmodule
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