29 lines
682 B
Systemverilog
29 lines
682 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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class Cls;
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rand int v_rand;
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int v_norand;
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task body;
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int x;
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v_norand = 42;
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x = this.randomize() with {v_rand==0;};
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`checkd(v_rand, 0);
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`checkd(v_norand, 42);
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endtask
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endclass
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module t;
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initial begin
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Cls c = new;
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c.body();
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$finish;
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end
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endmodule
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