51 lines
797 B
Systemverilog
51 lines
797 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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interface A;
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endinterface
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typedef virtual A a_t;
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typedef a_t a_array_t[6];
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class C;
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a_array_t vif;
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endclass
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module tb_top();
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A a[6](), b[6]();
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C c, d, e;
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a_array_t g;
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initial begin
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static a_t aa = a[0];
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b = a;
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c = new();
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c.vif = a;
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d = new();
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d.vif[0] = a[0];
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d.vif[1] = a[1];
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g[0] = a[0];
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g = a;
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d.vif[0] = g[0];
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d.vif = g;
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e = new();
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for (int i = 0; i < 6; ++i) begin
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e.vif[i] = g[i];
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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