verilator/test_regress/t/t_sys_rand_concat.py

#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

import vltest_bootstrap

test.scenarios('simulator')

test.compile()

test.execute()

for filename in test.glob_some(test.obj_dir + "/" + test.vm_prefix + "___024root__*__Slow.cpp"):
    test.file_grep_not(filename, r'(<<|>>)')

test.passes()