59 lines
2.3 KiB
Systemverilog
59 lines
2.3 KiB
Systemverilog
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// (C) 2001-2020, Daniel Kroening, Edmund Clarke,
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// Computer Science Department, University of Oxford
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// Computer Science Department, Carnegie Mellon University
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//
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// All rights reserved. Redistribution and use in source and binary forms, with
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// or without modification, are permitted provided that the following
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// conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the University nor the names of its contributors
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// may be used to endorse or promote products derived from this software
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// without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// You can contact the author at:
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// - homepage : https://www.cprover.org/ebmc/
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// - source repository : https://github.com/diffblue/hw-cbmc
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module main(input clk);
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reg [31:0] x = 0;
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always @(posedge clk)
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x<=x+1;
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// Starting from a particular state,
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// first_match yields the sequence that _ends_ first.
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// fails
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initial p0: assert property ((##1 1) or (##2 1) |-> x==1);
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// passes
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initial p1: assert property (first_match((##1 1) or (##2 1)) |-> x==1);
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// fails
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initial p2: assert property (1 or ##1 1 |-> x==0);
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// passes
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initial p3: assert property (first_match(1 or ##1 1) |-> x==0);
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endmodule
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