35 lines
804 B
Systemverilog
35 lines
804 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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class Foo;
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rand bit [65:0] m_wideUnpacked[3];
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constraint int_queue_c {
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m_wideUnpacked[0] == 0;
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m_wideUnpacked[1] == 1;
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m_wideUnpacked[2] == 2;
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}
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function void self_check();
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if (m_wideUnpacked[0] != 0) $stop;
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if (m_wideUnpacked[1] != 1) $stop;
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if (m_wideUnpacked[2] != 2) $stop;
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endfunction
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endclass
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module t;
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int success;
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initial begin
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Foo foo = new;
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success = foo.randomize();
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if (success != 1) $stop;
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foo.self_check();
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$display("Unpacked: %p", foo.m_wideUnpacked);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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