2020-12-07 23:55:22 +01:00
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class Cls1;
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function int randomize;
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return 1;
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endfunction
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endclass
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class Cls2;
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function void randomize(int x);
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endfunction
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2023-04-01 16:50:27 +02:00
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function void srandom(int seed);
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endfunction
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2020-12-07 23:55:22 +01:00
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endclass
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2025-09-13 15:28:43 +02:00
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module t;
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2020-12-07 23:55:22 +01:00
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endmodule
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