32 lines
558 B
Systemverilog
32 lines
558 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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class A;
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rand int j;
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endclass
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class B;
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A a;
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rand int i;
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function new();
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a = new;
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i = 7;
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endfunction
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task r();
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if (a.randomize() with { j == i; } == 0) $stop;
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endtask
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endclass
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module t;
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initial begin
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B b = new;
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b.r();
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if (b.a.j != 7) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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