50 lines
860 B
Systemverilog
50 lines
860 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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package pkg;
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typedef enum logic [1:0] {
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INT,
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BLA,
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DUMMY
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} t_shadowed_enum;
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endpackage
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module sub
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import pkg::*;
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(
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input logic INT, // This is also in the pkg::t_shadowed_enum, but it shadows it
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output logic dummy_out
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);
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assign dummy_out = !INT;
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endmodule
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module t;
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logic my_wire;
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logic dummy_out;
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sub i_sub (
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.INT(my_wire),
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.dummy_out(dummy_out)
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);
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initial begin
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my_wire = 1'b0;
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repeat (2) begin
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my_wire = ~my_wire;
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#1ns;
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$display("my_wire = %b, dummy_out = %b", my_wire, dummy_out);
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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