2025-05-01 04:00:06 +02:00
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2025 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('vlt')
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test.lint(verilator_flags2=['-Wall -Wno-DECLFILENAME'],
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fails=True,
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expect_filename=test.golden_filename)
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test.extract(in_filename=test.top_filename,
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2025-09-14 14:43:52 +02:00
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out_filename=test.root + "/docs/gen/ex_PROCASSINIT_faulty.rst",
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2025-05-01 04:00:06 +02:00
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lines="26-32")
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test.extract(in_filename=test.top_filename,
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2025-09-14 14:43:52 +02:00
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out_filename=test.root + "/docs/gen/ex_PROCASSINIT_fixed.rst",
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2025-05-01 04:00:06 +02:00
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lines="36-45")
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test.extract(in_filename=test.golden_filename,
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2025-09-14 14:43:52 +02:00
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out_filename=test.root + "/docs/gen/ex_PROCASSINIT_msg.rst",
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2025-05-01 04:00:06 +02:00
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lines="1-9")
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test.passes()
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