2020-08-15 15:43:53 +02:00
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2020 by Yutetsu TAKATSUKASA
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2023-01-21 02:42:30 +01:00
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// SPDX-License-Identifier: Unlicense
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2020-08-15 15:43:53 +02:00
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`verilator_config
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hier_block -module "sub?"
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2023-11-03 12:55:53 +01:00
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hier_block -module "delay" // matches recursive modules
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