verilator/test_regress/t/t_gen_missing_bad2.v

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2022-11-05 16:40:34 +01:00
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2012 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t;
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if ($test$plusargs("BAD-non-constant")) begin
initial $stop;
end
case (1)
$test$plusargs("BAD-non-constant"): initial $stop;
endcase
endmodule