2019-10-01 01:48:01 +02:00
|
|
|
// DESCRIPTION: Verilator: Verilog Test module
|
|
|
|
|
//
|
2020-03-21 16:24:24 +01:00
|
|
|
// This file ONLY is placed under the Creative Commons Public Domain, for
|
|
|
|
|
// any use, without warranty, 2019 by Wilson Snyder.
|
|
|
|
|
// SPDX-License-Identifier: CC0-1.0
|
2019-10-01 01:48:01 +02:00
|
|
|
|
|
|
|
|
int a = -12'd1;
|
2020-01-21 12:17:31 +01:00
|
|
|
int b = 65536'd1;
|
|
|
|
|
int c = 1231232312312312'd1;
|
2023-02-05 20:06:03 +01:00
|
|
|
int e = 12'1;
|
|
|
|
|
int f = 12'0;
|
|
|
|
|
int g = 12'z;
|
|
|
|
|
int h = 12'x;
|
