20 lines
388 B
Systemverilog
20 lines
388 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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class cl #(type T= int);
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function void f();
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T obj = new;
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endfunction
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endclass
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virtual class vcl;
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endclass;
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module t;
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cl #(vcl) c = new;
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initial begin
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end
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endmodule
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