2020-05-10 21:01:43 +02:00
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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2025-09-13 15:28:43 +02:00
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module t;
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2020-05-10 21:01:43 +02:00
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2025-10-08 03:06:11 +02:00
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function int f;
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fork
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;
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join_any // Illegal 13.4.4
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return 0;
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endfunction
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2020-05-10 21:01:43 +02:00
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2025-10-08 03:06:11 +02:00
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int i;
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2020-05-10 21:01:43 +02:00
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2025-10-08 03:06:11 +02:00
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initial begin
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i = f();
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end
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2020-05-10 21:01:43 +02:00
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endmodule
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