2024-09-08 19:00:03 +02:00
|
|
|
#!/usr/bin/env python3
|
2006-08-26 13:35:28 +02:00
|
|
|
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
|
|
|
|
#
|
2024-01-01 09:19:59 +01:00
|
|
|
# Copyright 2024 by Wilson Snyder. This program is free software; you
|
2020-03-21 16:24:24 +01:00
|
|
|
# can redistribute it and/or modify it under the terms of either the GNU
|
2009-05-04 23:07:57 +02:00
|
|
|
# Lesser General Public License Version 3 or the Perl Artistic License
|
|
|
|
|
# Version 2.0.
|
2020-03-21 16:24:24 +01:00
|
|
|
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
2006-08-26 13:35:28 +02:00
|
|
|
|
2024-09-08 19:00:03 +02:00
|
|
|
import vltest_bootstrap
|
2018-05-08 02:42:28 +02:00
|
|
|
|
2024-09-08 19:00:03 +02:00
|
|
|
test.scenarios('vlt')
|
2006-08-26 13:35:28 +02:00
|
|
|
|
2024-09-08 19:00:03 +02:00
|
|
|
test.compile(make_top_shell=False,
|
|
|
|
|
make_main=False,
|
|
|
|
|
v_flags2=["-FI", test.t_dir + "/t_flag_fi_h.h", "--exe", test.pli_filename])
|
2006-08-26 13:35:28 +02:00
|
|
|
|
2024-09-08 19:00:03 +02:00
|
|
|
test.execute()
|
|
|
|
|
|
|
|
|
|
test.passes()
|