16 lines
436 B
Systemverilog
16 lines
436 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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/* verilator lint_off COVERIGN */
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module t;
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covergroup cgN with function sample (int addr, bit is_read);
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endgroup
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cgN cov = new();
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function void run();
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cov.sample(.addr(11), .is_read(1'b1));
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endfunction
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endmodule
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