2024-12-20 03:42:52 +01:00
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// DESCRIPTION: Verilator: Verilog Test module
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//
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2026-01-27 02:24:34 +01:00
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2008 Wilson Snyder
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2024-12-20 03:42:52 +01:00
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// SPDX-License-Identifier: CC0-1.0
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module m();
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module m_in_m;
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endmodule
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program p_in_m();
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endprogram
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interface i_in_m();
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endinterface
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endmodule
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interface i();
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interface i_in_i();
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endinterface
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program p_in_i();
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endprogram
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endinterface
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