2026-03-04 15:08:07 +01:00
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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2026-03-05 02:12:10 +01:00
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input logic a,
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input logic b,
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output logic [1:0] y
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2026-03-04 15:08:07 +01:00
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);
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logic [1:0] w;
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assign w[0] = a; // <--- Warning
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assign w[0] = b; // <--- Warning
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assign w[1] = 1'b0;
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assign y = w;
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endmodule
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