2025-04-07 05:42:49 +02:00
|
|
|
// DESCRIPTION: Verilator: Verilog Test module
|
|
|
|
|
//
|
2026-01-27 02:24:34 +01:00
|
|
|
// This file ONLY is placed under the Creative Commons Public Domain.
|
|
|
|
|
// SPDX-FileCopyrightText: 2025 Wilson Snyder
|
2025-04-07 05:42:49 +02:00
|
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
|
|
|
|
|
|
// Not super-sensical to have checker without module, but useful for --lint-only
|
|
|
|
|
|
|
|
|
|
checker check_equal (bit clk, int a, int b);
|
|
|
|
|
assert property (@(posedge clk) a == b);
|
|
|
|
|
endchecker
|