44 lines
936 B
Systemverilog
44 lines
936 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Yutetsu TAKATSUKASA.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Outputs
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hit,
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// Inputs
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clk
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);
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input clk;
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output logic hit;
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logic [31:0] addr;
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logic [11:0] match_item0, match_item1;
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int cyc;
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initial addr = 32'h380;
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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addr <= 32'h380 + cyc;
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match_item0 = 12'h 380 + cyc[11:0];
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match_item1 = 12'h 390 - cyc[11:0];
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if (cyc == 9) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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always_comb begin
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hit = 1;
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unique case (addr[11:0])
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match_item0: $display("match_item0");
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match_item1: $display("match_item1");
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default: hit = 0;
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endcase
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end
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endmodule
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