2022-09-02 20:31:13 +02:00
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// DESCRIPTION: Verilator: Verilog Test module
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//
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2026-01-27 02:24:34 +01:00
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2022 Geza Lore
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2022-09-02 20:31:13 +02:00
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// SPDX-License-Identifier: CC0-1.0
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module t;
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wire a;
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wire b;
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wire c;
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assign a = b;
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assign b = c;
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assign c = a;
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endmodule
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