2022-09-02 20:31:13 +02:00
|
|
|
// DESCRIPTION: Verilator: Verilog Test module
|
|
|
|
|
//
|
2026-01-27 02:24:34 +01:00
|
|
|
// This file ONLY is placed under the Creative Commons Public Domain.
|
|
|
|
|
// SPDX-FileCopyrightText: 2022 Geza Lore
|
2022-09-02 20:31:13 +02:00
|
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
|
|
|
|
|
|
module t;
|
|
|
|
|
wire a;
|
|
|
|
|
wire b;
|
|
|
|
|
wire c;
|
|
|
|
|
assign a = b;
|
|
|
|
|
assign b = c;
|
|
|
|
|
assign c = a;
|
|
|
|
|
endmodule
|