2023-07-17 15:52:37 +02:00
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// DESCRIPTION: Verilator: Verilog Test module
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//
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2026-01-27 02:24:34 +01:00
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2023 Antmicro Ltd
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2023-07-17 15:52:37 +02:00
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// SPDX-License-Identifier: CC0-1.0
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class foo;
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function void g(input integer x);
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f(x);
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endfunction
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function void f(inout integer x);
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endfunction
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endclass
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