2025-09-06 21:21:50 +02:00
|
|
|
// DESCRIPTION: Verilator: Verilog Test module
|
|
|
|
|
//
|
2026-01-27 02:24:34 +01:00
|
|
|
// This file ONLY is placed under the Creative Commons Public Domain
|
|
|
|
|
// SPDX-FileCopyrightText: 2025 Antmicro
|
2025-09-06 21:21:50 +02:00
|
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
|
|
|
|
|
|
package foo;
|
2025-12-21 03:46:43 +01:00
|
|
|
class bar #(
|
|
|
|
|
type T = int
|
|
|
|
|
);
|
|
|
|
|
endclass
|
|
|
|
|
endpackage
|
|
|
|
|
;
|
2025-09-06 21:21:50 +02:00
|
|
|
|
|
|
|
|
import foo::bar;
|