27 lines
495 B
Systemverilog
27 lines
495 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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Iface ifc();
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initial begin
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#1;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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interface Iface;
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int tck;
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int tdo;
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task tsk(input int data_i, output int data_o);
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@(posedge tck);
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data_o <= tdo;
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endtask
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endinterface
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