2025-02-14 00:33:12 +01:00
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// DESCRIPTION: Verilator: Verilog Test module
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//
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2026-01-27 02:24:34 +01:00
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Antmicro
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2025-02-14 00:33:12 +01:00
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// SPDX-License-Identifier: CC0-1.0
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`define FOO foo
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`define BAR bar
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`define QUX qux
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`define STRIFY `"`FOO``-```BAR``-```QUX```"
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`define NESTED_STRIFY `"`STRIFY```"
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`define EMPTY
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`define EMPTY_STRIFY `"`EMPTY```"
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`STRIFY
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`NESTED_STRIFY
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`EMPTY_STRIFY
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