verilator/test_regress/t/t_forceable_net.vlt

// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2021 Geza Lore
// SPDX-License-Identifier: CC0-1.0

`verilator_config

forceable -module "*" -var "net_*"
Implement 'forceable' attribute Using the 'forceable' directive in a configuration file, or the /* verilator forceable */ metacomment on a variable declaration will generate additional public signals that allow the specified signals to be forced/released from the C++ code. 2021-12-19 20:45:06 +01:00			`// DESCRIPTION: Verilator: Verilog Test module`
			`//`
Add SPDX copyright identifiers, and get 'reuse' clean. No functional change. 2026-01-27 02:24:34 +01:00			`// This file ONLY is placed under the Creative Commons Public Domain.`
			`// SPDX-FileCopyrightText: 2021 Geza Lore`
Implement 'forceable' attribute Using the 'forceable' directive in a configuration file, or the /* verilator forceable */ metacomment on a variable declaration will generate additional public signals that allow the specified signals to be forced/released from the C++ code. 2021-12-19 20:45:06 +01:00			`// SPDX-License-Identifier: CC0-1.0`

			`verilator_config

			`forceable -module "" -var "net_"`