2021-03-07 19:52:37 +01:00
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%Error: t/t_wire_self_bad.v:11:16: Wire inputs its own output, creating circular logic (wire x=x)
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11 | wire myself = myself;
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2025-04-05 23:10:28 +02:00
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... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
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2021-03-07 19:52:37 +01:00
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%Error: Exiting due to
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