verilator/test_regress/t/t_vlt_legacy.v

// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0

module t (
    input clk /*verilator clock_enable*/
);
  initial $finish;
endmodule