35 lines
755 B
Systemverilog
35 lines
755 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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const static int a1;
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const static int a2 = 0;
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initial begin
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const static int c1;
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const static int c2 = 0;
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const automatic int d1;
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const automatic int d2 = 0;
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end
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function static void tb_func1();
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const static int e1;
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const static int e2 = 0;
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const automatic int f1;
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const automatic int f2 = 0;
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endfunction
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function automatic void tb_func2();
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const static int g1;
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const static int g2 = 0;
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const automatic int h1;
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const automatic int h2 = 0;
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endfunction
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endmodule
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