2024-09-08 19:00:03 +02:00
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#!/usr/bin/env python3
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2024-01-28 15:05:50 +01:00
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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2024-09-08 19:00:03 +02:00
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import vltest_bootstrap
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test.scenarios('simulator')
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test.top_filename = "t/t_unopt_converge.v"
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2024-01-28 15:05:50 +01:00
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2025-10-25 17:00:25 +02:00
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test.compile(
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v_flags2=['+define+ALLOW_UNOPT', '--output-split 0', '-fno-dfg', '--converge-limit 5'])
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2024-09-08 19:00:03 +02:00
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if test.vlt_all:
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test.execute(fails=True, expect_filename=test.golden_filename)
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2024-09-08 19:00:03 +02:00
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test.passes()
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