18 lines
452 B
Systemverilog
18 lines
452 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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primitive udp_1(output reg o, input i);
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table
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? : 0 0 : 0; // <--- BAD too many recirc
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endtable
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endprimitive
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primitive udp_2(output reg o, input i);
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table
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? : 0 : 0 0; // <--- BAD too many outputs
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endtable
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endprimitive
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